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BF1202_10 Datasheet, PDF (8/15 Pages) NXP Semiconductors – N-channel dual-gate PoLo MOS-FETs
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NXP Semiconductors
N-channel dual-gate PoLo MOS-FETs
Product specification
BF1202; BF1202R; BF1202WR
102
handbook, halfpage
Yis
(mS)
10
1
MCD964
bis
gis
103
handbook, halfpage
yrs
(μS)
102
10
MCD965 −103
ϕrs
(deg)
ϕrs
−102
yrs
−10
10−1
10
102
103
f (GHz)
VDS = 5 V; VG2 = 4 V.
ID = 12 mA; Tamb = 25 C.
Fig.17 Input admittance as a function of frequency;
typical values.
1
10
−1
102
103
f (MHz)
VDS = 5 V; VG2 = 4 V.
ID = 12 mA; Tamb = 25 C.
Fig.18 Reverse transfer admittance and phase as
a function of frequency; typical values.
102
handbook, halfpage
yfs
(mS)
10
MCD966 −102
10
handbook, halfpage
ϕfs
Yos
yfs
(deg)
(mS)
1
−10
ϕfs
10−1
MCD967
bos
gos
1
10
−1
102
103
f (MHz)
VDS = 5 V; VG2 = 4 V.
ID = 12 mA; Tamb = 25 C.
Fig.19 Forward transfer admittance and phase as
a function of frequency; typical values.
10−2
10
102
103
f (MHz)
VDS = 5 V; VG2 = 4 V.
ID = 12 mA; Tamb = 25 C.
Fig.20 Output admittance as a function of
frequency; typical values.
2010 Sep 16
8
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