BF1202_10 Datasheet, PDF (7/15 Pages) NXP Semiconductors – N-channel dual-gate PoLo MOS-FETs

NXP Semiconductors
N-channel dual-gate PoLo MOS-FETs
Product specification
BF1202; BF1202R; BF1202WR
40
handbook, halfpage
IG1
(μA)
30
20
10
MCD960
VGG = 5 V
4.5 V
4V
3.5 V
3V
0
0
2
4
6
VG2-S (V)
V_DS = 5 V; T_j = 25 C.
R_G1 = 120 k (connected to V_GG); see Fig.21.
Fig.13 Gate 1 current as a function of gate 2
voltage; typical values.
0
hand_gb_ao_io_nk, halfpage
reduction
(dB)
−10
MCD961
−20
−30
−40
−50
0
1
2
3
4
VAGC (V)
V_DS = 5 V; V_GG = 5 V; R_G1 = 120 k;
f = 50 MHz; T_amb = 25 C.
Fig.14 Typical gain reduction as a function of the
AGC voltage; see Fig.21.
handboo¹k,²h⁰alfpage
Vunw
(dBμV)
110
MCD962
handbook,¹h⁶alfpage
ID
(mA)
12
MCD963
100
8
90
4
80
0
10
20
30
40
50
gain reduction (dB)
V_DS = 5 V; V_GG = 5 V; R_G1 = 120 k;
f= 50 MHz; f_unw = 60 MHz; T_amb = 25 C.
Fig.15 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; Fig.21.
0
0
10
20
30
40
50
gain reduction (dB)
V_DS = 5 V; V_GG = 5 V; R_G1 = 120 k;
f = 50 MHz; T_amb = 25 C.
Fig.16 Drain current as a function of gain
reduction; typical values; see Fig.21.
2010 Sep 16
7