ISP1562 Datasheet, PDF (72/94 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus PCI Host Controller

NXP Semiconductors
ISP1562
HS USB PCI host controller
Table 109. PORTSC 1, 2 - Port Status and Control 1, 2 register bit description
Address: Content of the base address register + 64h + (4 × Port Number − 1) where Port Number is 1, 2
Bit
Symbol
Description
31 to 23 reserved
-
22
WKOC_E
Wake on Overcurrent Enable: Default = 0. Setting this bit enables the port to be sensitive to
overcurrent conditions as wake-up events.^[1]
21
WKDS
Wake on Disconnect Enable: Default = 0. Setting this bit enables the port to be sensitive to
CNNT_E
device disconnects as wake-up events.^[1]
20
WKCNNT_E Wake on Connect Enable: Default = 0. Setting this bit enables the port to be sensitive to
device connects as wake-up events.^[1]
19 to 16 PTC[3:0]
Port Test Control: Default = 0000b. When this field is logic 0, the port is not operating in test
mode. A nonzero value indicates that it is operating in test mode and test mode is indicated by
the value. The encoding of the test mode bits are:
0000b — Test mode disabled
0001b — Test J_STATE
0010b — Test K_STATE
0011b — Test SE0_NAK
0100b — Test packet
0101b — Test FORCE_ENABLE
0110b to 1111b — reserved
15 to 14 reserved
-
13
PO
Port Owner: Default = 1. This bit unconditionally goes to logic 0 when CF (bit 0) in the
CONFIGFLAG register makes logic 0 to logic 1 transition. This bit unconditionally goes to
logic 1 when the CF bit is logic 0. The system software uses this field to release ownership of
the port to a selected host controller, if the attached device is not a high-speed device. Software
writes logic 1 to this bit, if the attached device is not a high-speed device. Logic 1 in this bit
means that a companion host controller owns and controls the port.
12
PP
Port Power: The function of this bit depends on the value of PPC (bit 4) in the HCSPARAMS
register.
If PPC = 0 and PP = 1 — The host controller does not have port power control switches.
Always powered.
If PPC = 1 and PP = 1 or 0 — The host controller has port power control switches. This bit
represents the current setting of the switch: logic 0 = off, logic 1 = on. When PP is logic 0, the
port is nonfunctional and will not report any status.
When an overcurrent condition is detected on a powered port and PPC is logic 1, the PP bit in
each affected port may be changed by the host controller from logic 1 to logic 0, removing
power from the port.
11 to 10 LS[1:0]
Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10)
signal lines. These bits are used to detect low-speed USB devices before the port reset and
enable sequence. This field is valid only when the Port Enable bit is logic 0, and the Current
Connect Status bit is set to logic 1.
00b — SE0: Not a low-speed device, perform EHCI reset
01b — K-state: Low-speed device, release ownership of port
10b — J-state: Not a low-speed device, perform EHCI reset
11b — Undefined: Not a low-speed device, perform EHCI reset
If the PP bit is logic 0, this field is undefined.
9
reserved
-
ISP1562_3
Product data sheet
Rev. 03 — 14 November 2008
© NXP B.V. 2008. All rights reserved.
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