ISP1562 Datasheet, PDF (36/94 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus PCI Host Controller

NXP Semiconductors
ISP1562
HS USB PCI host controller
Table 46. HcControl - Host Controller Control register bit description
Address: Content of the base address register + 04h
Bit
Symbol Description
31 to 11 reserved -
10
RWE
Remote Wake-up Enable: This bit is used by the HCD to enable or disable the remote wake-up
feature on detecting upstream resume signaling. When this bit and RD (bit 3) in the HcInterruptStatus
register are set, a remote wake-up is signaled to the host system. Setting this bit has no impact on
the generation of hardware interrupt.
9
RWC
Remote Wake-up Connected: This bit indicates whether the host controller supports remote
wake-up signaling. If remote wake-up is supported and used by the system, it is the responsibility of
the system firmware to set this bit during POST. The host controller clears the bit on a hardware reset
but does not alter it on a software reset. Remote wake-up signaling of the host system is
host-bus-specific and is not described in this specification.
8
IR
Interrupt Routing: This bit determines the routing of interrupts generated by events registered in
HcInterruptStatus. If clear, all interrupts are routed to the normal host bus interrupt mechanism. If set,
interrupts are routed to the system management interrupt. The HCD clears this bit on a hardware
reset, but it does not alter this bit on a software reset. The HCD uses this bit as a tag to indicate the
ownership of the host controller.
7 to 6
HCFS
[1:0]
Host Controller Functional State for USB:
00b — USBRESET
01b — USBRESUME
10b — USBOPERATIONAL
11b — USBSUSPEND
A transition to USBOPERATIONAL from another state causes SOF generation to begin 1 ms later.
The HCD may determine whether the host controller has begun sending SOFs by reading SF (bit 2)
in HcInterruptStatus.
This field may be changed by the host controller only when in the USBSUSPEND state. The host
controller may move from the USBSUSPEND state to the USBRESUME state after detecting the
resume signaling from a downstream port.
The host controller enters USBSUSPEND after a software reset; it enters USBRESET after a
hardware reset. The latter also resets the root hub and asserts subsequent reset signaling to
downstream ports.
5
BLE
Bulk List Enable: This bit is set to enable the processing of the bulk list in the next frame. If cleared
by the HCD, processing of the bulk list does not occur after the next SOF. The host controller checks
this bit whenever it wants to process the list. When disabled, the HCD may modify the list. If
HcBulkCurrentED is pointing to an Endpoint Descriptor (ED) to be removed, the HCD must advance
the pointer by updating HcBulkCurrentED before re-enabling processing of the list.
4
CLE
Control List Enable: This bit is set to enable the processing of the control list in the next frame. If
cleared by the HCD, processing of the control list does not occur after the next SOF. The host
controller must check this bit whenever it wants to process the list. When disabled, the HCD may
modify the list. If HcControlCurrentED is pointing to an ED to be removed, the HCD must advance the
pointer by updating HcControlCurrentED before re-enabling processing of the list.
3
IE
Isochronous Enable: This bit is used by the HCD to enable or disable processing of isochronous
EDs. While processing the periodic list in a frame, the host controller checks the status of this bit
when it finds an isochronous ED (that is, the Format bit of ED is logic 1; for details, refer to Open Host
Controller Interface Specification for USB Rev. 1.0a). If set (enabled), the host controller continues
processing the EDs. If cleared (disabled), the host controller halts processing of the periodic list,
which now contains only isochronous EDs, and begins processing the bulk or control lists. Setting this
bit is guaranteed to take effect in the next frame and not the current frame.
2
PLE
Periodic List Enable: This bit is set to enable the processing of the periodic list in the next frame. If
cleared by the HCD, processing of the periodic list does not occur after the next SOF. The host
controller must check this bit before it starts processing the list.
ISP1562_3
Product data sheet
Rev. 03 — 14 November 2008
© NXP B.V. 2008. All rights reserved.
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