ISP1562 Datasheet, PDF (44/94 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus PCI Host Controller

NXP Semiconductors
ISP1562
HS USB PCI host controller
Table 57. HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit allocation
Address: Content of the base address register + 1Ch
Bit
31
30
29
28
27
26
25
24
Symbol
PCED[27:20]
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit
23
22
21
20
19
18
17
16
Symbol
PCED[19:12]
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit
15
14
13
12
11
10
9
8
Symbol
PCED[11:4]
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit
7
6
5
4
3
2
1
0
Symbol
PCED[3:0]
reserved
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Table 58. HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit description
Address: Content of the base address register + 1Ch
Bit
Symbol
Description
31 to 4
PCED[27:0]
Period Current ED: This is used by the host controller to point to the head of one of the periodic
lists that must be processed in the current frame. The content of this register is updated by the
host controller after a periodic ED is processed. The HCD may read the content in determining
which ED is being processed at the time of reading.
3 to 0 reserved
-
11.1.9 HcControlHeadED register
The HcControlHeadED register contains the physical address of the first ED of the control
list. The bit allocation is given in Table 59.
Table 59. HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit allocation
Address: Content of the base address register + 20h
Bit
31
30
29
28
27
26
25
24
Symbol
CHED[27:20]
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit
23
22
21
20
19
18
17
16
Symbol
CHED[19:12]
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit
15
14
13
12
11
10
9
8
Symbol
CHED[11:4]
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
ISP1562_3
Product data sheet
Rev. 03 — 14 November 2008
© NXP B.V. 2008. All rights reserved.
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