TDA8922C Datasheet, PDF (7/40 Pages) NXP Semiconductors – 2 X 75 W class-D power amplifier

NXP Semiconductors
TDA8922C
2 × 75 W class-D power amplifier
To ensure the coupling capacitors at the inputs (C_IN in Figure 10) are fully charged before
the outputs start switching, a delay is inserted during the transition from Mute to Operating
mode. An overview of the start-up timing is provided in Figure 5.
V_MODE
> 4.2 V
(1)
50 %
duty cycle
audio output
modulated PWM
operating
2.1 V < V_MODE < 2.9 V
mute
0 V (SGND) ^standby
100 ms
> 350 ms
time
50 ms
V_MODE
> 4.2 V
(1)
50 %
duty cycle
audio output
modulated PWM
operating
2.1 V < V_MODE < 2.9 V
mute
0 V (SGND) ^standby
100 ms
50 ms
> 350 ms
time
010aaa584
(1) First ¹â„₄ pulse down.
Upper diagram: When switching from Standby to Mute, there is a delay of approximately 100 ms
before the output starts switching. The audio signal will become available once V_MODE reaches the
Operating mode level (see Table 8), but not earlier than 150 ms after switching to Mute. To start-up
pop noise-free, it is recommended that the time constant applied to pin MODE be at least 350 ms
for the transition between Mute and Operating modes.
Lower diagram: When switching directly from Standby to Operating mode, there is a delay of
100 ms before the outputs start switching. The audio signal becomes available after a second
delay of 50 ms. To start-up pop noise-free, it is recommended that the time-constant applied to pin
MODE be at least 500 ms for the transition between Standby and Operating modes.
Fig 5. Timing on mode selection input pin MODE
TDA8922C_1
Product data sheet
Rev. 01 — 7 September 2009
© NXP B.V. 2009. All rights reserved.
7 of 40