PCAL9539A Datasheet, PDF (7/48 Pages) NXP Semiconductors – Low-voltage 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset

NXP Semiconductors
PCAL9539A
16-bit I²C-bus and SMBus low power I/O port with interrupt and reset
6.2.2 Input port register pair (00h, 01h)
The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by the Configuration
register. The Input port registers are read only; writes to these registers have no effect.
The default value ‘X’ is determined by the externally applied logic level. An Input port
register read operation is performed as described in Section 7.2 “Reading the port
registers”.
Table 5. Input port 0 register (address 00h)
Bit
7
6
5
4
3
2
1
0
Symbol I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
Default
X
X
X
X
X
X
X
X
Table 6. Input port 1 register (address 01h)
Bit
7
6
5
4
3
2
1
0
Symbol I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
Default
X
X
X
X
X
X
X
X
6.2.3 Output port register pair (02h, 03h)
The Output port registers (registers 2 and 3) show the outgoing logic levels of the pins
defined as outputs by the Configuration register. Bit values in these registers have no
effect on pins defined as inputs. In turn, reads from these registers reflect the value that
was written to these registers, not the actual pin value. A register pair write is described in
Section 7.1 and a register pair read is described in Section 7.2.
Table 7.
Bit
Symbol
Default
Output port 0 register (address 02h)
7
6
5
4
O0.7
O0.6
O0.5
O0.4
1
1
1
1
3
O0.3
1
2
O0.2
1
1
O0.1
1
0
O0.0
1
Table 8.
Bit
Symbol
Default
Output port 1 register (address 03h)
7
6
5
4
O1.7
O1.6
O1.5
O1.4
1
1
1
1
3
O1.3
1
2
O1.2
1
1
O1.1
1
0
O1.0
1
PCAL9539A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
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