PCAL9539A Datasheet, PDF (5/48 Pages) NXP Semiconductors – Low-voltage 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset

NXP Semiconductors
PCAL9539A
16-bit I²C-bus and SMBus low power I/O port with interrupt and reset
Table 3.
Symbol
P1_6^[3]
P1_7^[3]
A0
SCL
Pin description …continued
Pin
Type
TSSOP24 HWQFN24
19
16
I/O
20
17
I/O
21
18
I
22
19
I
SDA
23
20
I/O
V_DD
24
21
power
Description
Port 1 input/output 6.
Port 1 input/output 7.
Address input 0. Connect directly to V_DD or V_SS.
Serial clock bus. Connect to V_DD through a
pull-up resistor.
Serial data bus. Connect to V_DD through a
pull-up resistor.
Supply voltage.
[1] HWQFN24 package die supply ground is connected to both V_SS pin and exposed center pad. V_SS pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
[2] Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-up, all I/O are configured as high-impedance
inputs.
[3] Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-up, all I/O are configured as high-impedance
inputs.
6. Functional description
Refer to Figure 1 “Block diagram of PCAL9539A”.
6.1 Device address
slave address
1 1 1 0 1 A1 A0 R/W
fixed
hardware
selectable
002aah062
Fig 4. PCAL9539A device address
A1 and A0 are the hardware address package pins and are held to either HIGH (logic 1)
or LOW (logic 0) to assign one of the four possible slave addresses. The last bit of the
slave address (R/W) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Registers
6.2.1 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCAL9539A. The lower
three bits of this data byte state the operation (read or write) and the internal registers
PCAL9539A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
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