PCAL9539A Datasheet, PDF (22/48 Pages) NXP Semiconductors – Low-voltage 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset

NXP Semiconductors
PCAL9539A
16-bit I²C-bus and SMBus low power I/O port with interrupt and reset
V_DD
3.3 V
5V
V_DD
Pn
LED
100 kΩ
V_DD
LED
Pn
002aag164
Fig 14. High value resistor in parallel with
the LED
002aag165
Fig 15. Device supplied by a lower voltage
8.2 Output drive strength control
The Output drive strength registers allow the user to control the output drive level of the
GPIO. Each GPIO can be configured independently to one of the four possible output
current levels. By programming these bits the user is changing the number of transistor
pairs or ‘fingers’ that drive the I/O pad.
Figure 16 shows a simplified output stage. The behavior of the pad is affected by the
Configuration register, the output port data, and the current control register. When the
Current Control register bits are programmed to 10b, then only two of the fingers are
active, reducing the current drive capability by 50 %.
PMOS_EN0
V_DD
Current Control
register
DECODER
PMOS_EN[3:0]
NMOS_EN[3:0]
Configuration
register
PMOS_EN1
PMOS_EN2
PMOS_EN3
Output port
register
NMOS_EN3
NMOS_EN2
NMOS_EN1
Fig 16. Simplified output stage
PCAL9539A
Product data sheet
NMOS_EN0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 October 2012
P0_0 to P0_7
P1_0 to P1_7
002aah431
© NXP B.V. 2012. All rights reserved.
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