BUK127-50DL Datasheet, PDF (7/11 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK127-50DL
VISR / V
3
BUK127-50DL
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
-50 -25
0
25
50
75
100 125
150
Tj / C
Fig.14. Typical Protection reset voltage.
V_ISR = f(T_j); t_lr = 100 µs.
ID / mA
400
BUK127-50DL
VIS & VDS / V
15
10
VIS
5
BUK127-50DL
VDS
0
-40 -20 0 20 40 60 80 100 120 140 160
time / us
Fig.17. Typical switching waveforms, resistive load .
R_L = 50 Ω; adjust V_DD to obtain I_D = 250 mA; T_j = 25˚C
IDSS
10 uA
BUK127-50DL
300
200
TYP.
100
1 uA
100 nA
0
56
58
60
62
64
66
68
VDS / V
Fig.15. Overvoltage clamping characteristic, 25˚C.
I_D = f(V_DS); conditions: V_IS = 0 V; t_p ≤ 300 µs
VDD
10 nA
-50
0
50
100
150
Tj / C
Fig.18. Typical drain source leakage current
I_DSS = f(T_j); conditions: V_DS = 40 V; V_IS = 0 V.
RL
D
TOPFET
VDS
measure
I
P
D.U.T.
VIS
S
0V
Fig.16. Test circuit for resistive load switching times.
V_IS = 5 V
October 2001
7
Rev 1.011