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| BUK127-50DL Datasheet, PDF (3/11 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET | |||
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Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK127-50DL
OUTPUT CHARACTERISTICS
Limits are for -40ËC ⤠Tmb ⤠150ËC; typicals are for Tmb = 25 ËC unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
Off-state
VIS = 0 V
V(CL)DSS Drain-source clamping voltage ID = 10 mA
50
ID = 200 mA; tp ⤠300 µs; δ ⤠0.01
50
IDSS
Drain source leakage current VDS = 40 V
-
Tmb = 25 ËC
-
On-state
VIS ⥠4 V; tp ⤠300 µs; δ ⤠0.01
RDS(ON)
Drain-source resistance
ID = 100 mA
-
Tmb = 25 ËC
-
TYP.
-
60
-
0.1
-
150
MAX. UNIT
-
V
70
V
100 µA
10 µA
380 mâ¦
200 mâ¦
INPUT CHARACTERISTICS
The supply for the logic and overload protection is taken from the input.
Limits are for -40ËC ⤠Tmb ⤠150ËC; typicals are for Tmb = 25ËC unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
VIS(TO)
IIS
IISL
VISR
tlr
V(CL)IS
RIG
Input threshold voltage
Input supply current
Input supply current
Protection reset voltage1
Latch reset time
Input clamping voltage
Input series resistance2
to gate of power MOSFET
VDS = 5 V; ID = 1 mA
0.6
Tmb = 25ËC 1.1
normal operation;
VIS = 5 V
100
VIS = 4 V
80
protection latched;
VIS = 5 V
200
VIS = 3 V
130
reset time tr ⥠100 µs
1.5
VIS1 = 5 V, VIS2 < 1 V
10
II = 1.5 mA
5.5
Tmb = 25ËC
-
TYP.
-
1.6
220
195
400
250
2
40
-
33
MAX. UNIT
2.4 V
2.1 V
400 µA
330 µA
650 µA
430 µA
2.9 V
100 µs
8.5 V
-
kâ¦
1 The input voltage below which the overload protection circuits will be reset.
2 Not directly measureable from device terminals.
October 2001
3
Rev 1.011
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