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BUK114-50L Datasheet, PDF (7/13 Pages) NXP Semiconductors – Logic level TOPFET
Philips Semiconductors
Logic level TOPFET
SMD version of BUK104-50L/S
Product specification
BUK114-50L/S
120 PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.4. Normalised limiting power dissipation.
PD% = 100⋅PD/PD(25 ˚C) = f(Tmb)
ID%
120
Normalised Current Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.5. Normalised continuous drain current.
ID% = 100⋅ID/ID(25 ˚C) = f(Tmb); conditions: VIS = 5 V
ID & IDM / A
100
RDS(ON) = VDS/ID
10
DC
1
BUK114-50L/S
tp =
10 us
100 us
1 ms
10 ms
100 ms
Overload protection characteristics not shown
0.1
1
10
100
VDS / V
Fig.6. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Zth / (K/W)
10
BUK114-50L/S
D=
0.5
1
0.2
0.1
0.05
0.1 0.02
PD
tp
D=
tp
T
0
0.01
1E-07
1E-05
1E-03
t/s
T
t
1E-01
Fig.7. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
1E+01
ID / A
50
40
30
20
BUK114-50L/S
VIS / V =
10
9
8
7
6
5
4
10
3
2
0
0
4
8
12
16
20
24
28
32
VDS / V
Fig.8. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VIS; tp = 250 µs & tp < td sc
ID / A
20
15
10
VIS / V = 10
BUK114-50L/S
7
6
5
4
5
3
0
0
1
2
VDS / V
Fig.9. Typical on-state characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VIS; tp = 250 µs
September 1996
7
Rev 1.000