BUK114-50L Datasheet, PDF (5/13 Pages) NXP Semiconductors – Logic level TOPFET

Philips Semiconductors
Logic level TOPFET
SMD version of BUK104-50L/S
Product specification
BUK114-50L/S
INPUT CHARACTERISTICS
T_mb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
Normal operation
V_IS(TO)
Input threshold voltage
I_IS
V_(CL)IS
R_ISL
Input current
Input clamp voltage
Overload protection latched
Input resistance¹
Application information
External input resistances for
R_IS
internal overvoltage clamping²
R_I
internal overload protection³
CONDITIONS
V_DS = 5 V; I_D = 1 mA
T_mb = 150 ˚C
V_IS = 10 V
I_I = 1 mA
V_PS = 5 V
V_PS = 10 V
(see figure 29)
R_I = ∞ Ω;
R_IS = ∞ Ω;
I_I = 5 mA;
T_mb = 150 ˚C
I_I = 5 mA;
T_mb = 150 ˚C
V_DS > 30 V
V_II = 5 V
V_II = 10 V
MIN. TYP. MAX. UNIT
1.0 1.5 2.0 V
0.5
-
-
V
-
10 100 nA
11 13
-
V
-
55
-
Ω
-
95
-
Ω
-
35
-
Ω
-
60
-
Ω
100 -
1
-
2
-
-
Ω
-
kΩ
-
kΩ
SWITCHING CHARACTERISTICS
T_mb = 25 ˚C; R_I = 50 Ω; R_IS = 50 Ω (see figure 29); resistive load R_L = 10 Ω. For waveforms see figure 28.
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX.
t_{d on}
Turn-on delay time
t_r
Rise time
t_{d off}
Turn-off delay time
t_f
Fall time
V_DD = 15 V; V_IS: 0 V ⇒ 10 V
V_DD = 15 V; V_IS: 10 V ⇒ 0 V
-
8
-
-
13
-
- 100 -
-
45
-
UNIT
ns
ns
ns
ns
CAPACITANCES
T_mb = 25 ˚C; f = 1 MHz
SYMBOL PARAMETER
C_iss
Input capacitance
C_oss
Output capacitance
C_rss
Reverse transfer capacitance
C_pso
Protection supply pin
capacitance
C_fso
Flag pin capacitance
CONDITIONS
V_DS = 25 V; V_IS = 0 V
V_DS = 25 V; V_IS = 0 V
V_DS = 25 V; V_IS = 0 V
V_PS = 10 V
V_FS = 10 V; V_PS = 0 V
MIN.
-
-
-
-
TYP.
415
275
55
30
MAX.
600
400
80
-
UNIT
pF
pF
pF
pF
-
20
-
pF
1 The resistance of the internal transistor which discharges the power MOSFET gate capacitance when overload protection operates.
The external drive circuit should be such that the input voltage does not exceed V_IS(TO) minimum when the overload protection has
operated. Refer also to figure for latched input characteristics.
2 Applications using a lower value for R_IS would require external overvoltage protection.
3 For applications requiring a lower value for R_I, an external overload protection strategy is possible using the flag pin to ‘tell’ the control circuit to
switch off the input.
September 1996
5
Rev 1.000