BUK108-50DL Datasheet, PDF (7/10 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK108-50DL
IISL & IIS / uA
600
BUK108-50DL
500
PROTECTION LATCHED
400
IISL
300
RESET
IIS
200
100
NORMAL
0
0
2
4
6
VIS / V
Fig.14. Typical DC input characteristics, T_j = 25 ˚C.
I_ISL & I_IS = f(V_IS); protection latched & normal operation
IS / A
60
BUK108-50DL
50
40
30
20
10
0
0
0.2
0.4
0.6
0.8
1
1.2 1.4
VSD / V
Fig.15. Typical reverse diode current, T_j = 25 ˚C.
I_S = f(V_SDS); conditions: V_IS = 0 V; t_p = 250 µs
VDD
RL
D
TOPFET
I
P
D.U.T.
RI
VIS
S
ID measure
0V
0R1
Fig.16. Test circuit for resistive load switching times.
VIS / V & VDS / V
VDS
10
VIS
5
BUK108-50DL
0
0
100
200
300
400
time / us
Fig.17. Typical switching waveforms, resistive load.
V_DD = 13 V; R_L = 4 Ω; R_I = 50 Ω, T_j = 25 ˚C.
EDSM%
120
110
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80 100 120 140
Tmb / C
Fig.18. Normalised limiting clamping energy.
E_DSM% = f(T_mb); conditions: I_D = 15 A; V_IS = 5 V
VDS
0
ID
0
VIS
0
V(CL)DSS
VDD
L
+ ^VDD
VDS
D
TOPFET
I
P
D.U.T.
-
-ID/100
RIS
Schottky
S
R 01
shunt
Fig.19. Clamping energy test circuit, R_IS = 50 Ω.
E_DSM = 0.5 ⋅ L I_D² ⋅ V_(CL)DSS/(V_(CL)DSS − V_DD)
June 1996
7
Rev 1.000