BUK108-50DL Datasheet, PDF (6/10 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK108-50DL
a
1.5
Normalised RDS(ON) = f(Tj)
1.0
0.5
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.8. Normalised drain-source on-state resistance.
a = R_DS(ON)/R_DS(ON)25 ˚C = f(T_j); I_D = 7.5 A; V_IS = 5 V
td sc / ms
100
BUK108-50DL
10
PDSM
1
0.1
0.01
0.1
1
PDS / kW
Fig.9. Typical overload protection characteristics.
t_{d sc} = f(P_DS); conditions: V_IS ≥ 4 V; T_j = 25 ˚C.
PDSM%
120
100
80
60
40
20
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tmb / C
Fig.10. Normalised limiting overload dissipation.
P_DSM% =100⋅P_DSM/P_DSM(25 ˚C) = f(T_mb)
Energy & Time
1
0.5
Time / ms
BUK108-50DL
Energy / J
Tj(TO)
0
-60 -20
20
60 100 140 180 220
Tmb / C
Fig.11. Typical overload protection characteristics.
Conditions: V_DD = 13 V; V_IS = 5 V; SC load = 30 mΩ
ID / A
20
BUK108-50DL
15
typ.
10
5
0
50
60
70
VDS / V
Fig.12. Typical clamping characteristics, 25 ˚C.
I_D = f(V_DS); conditions: V_IS = 0 V; t_p ≤ 50 µs
VIS(TO) / V
2
1
max.
typ.
min.
0
-60 -40 -20 0
20 40 60 80 100 120 140
Tj / C
Fig.13. Input threshold voltage.
V_IS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = 5 V
June 1996
6
Rev 1.000