MK80FN256VLL15 Datasheet, PDF (67/95 Pages) NXP Semiconductors – High performance ARM® Cortex®-M4F MCU with up to 256KB of Flash, 256KB of SRAM, Full Speed USB connectivity, and QuadSPI for interfacing to Serial NOR flash

Peripheral operating requirements and behaviors
3.7.9 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 56. SDHC full voltage range switching specifications
Num
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
Symbol Description
Min.
Max.
Operating voltage
1.71
3.6
Card input clock
fpp
Clock frequency (low speed)
0
400
fpp
Clock frequency (SD\SDIO full speed\high speed)
0
25/45
fpp
Clock frequency (MMC full speed\high speed)
0
25/45
f_OD
Clock frequency (identification mode)
0
400
t_WL
Clock low time
7
—
t_WH
Clock high time
7
—
t_TLH
Clock rise time
—
3
t_THL
Clock fall time
—
3
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
t_OD
SDHC output delay (output valid)
0
8.1
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
t_ISU
SDHC input setup time
t_IH
SDHC input hold time
5
—
0
—
Unit
V
kHz
MHz
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
Num
SD1
SD2
SD3
SD4
SD5
SD6
Table 57. SDHC limited voltage range switching specifications
Symbol Description
Min.
Max.
Operating voltage
2.7
3.6
Card input clock
fpp
Clock frequency (low speed)
0
400
fpp
Clock frequency (SD\SDIO full speed\high speed)
0
25\50
fpp
Clock frequency (MMC full speed\high speed)
0
20\50
f_OD
Clock frequency (identification mode)
0
400
t_WL
Clock low time
7
—
t_WH
Clock high time
7
—
t_TLH
Clock rise time
—
3
t_THL
Clock fall time
—
3
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
t_OD
SDHC output delay (output valid)
0
7
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
Table continues on the next page...
Unit
V
kHz
MHz
MHz
kHz
ns
ns
ns
ns
ns
Kinetis K80 Sub-Family, Rev.4, 09/2015.
67
Freescale Semiconductor, Inc.