MK80FN256VLL15 Datasheet, PDF (45/95 Pages) NXP Semiconductors – High performance ARM® Cortex®-M4F MCU with up to 256KB of Flash, 256KB of SRAM, Full Speed USB connectivity, and QuadSPI for interfacing to Serial NOR flash

Peripheral operating requirements and behaviors
3. D7 and D8 are for write cycles only.
Table 36. SDRAM Timing (Limited voltage range)
NUM
D0
D1
D2
D3
D4
D5
D6
D7³
D8³
Characteristic ¹
Operating voltage
Frequency of operation
Clock period
CLKOUT high to SDRAM address valid
CLKOUT high to SDRAM control valid
CLKOUT high to SDRAM address invalid
CLKOUT high to SDRAM control invalid
SDRAM data valid to CLKOUT high
CLKOUT high to SDRAM data invalid
CLKOUT high to SDRAM data valid
CLKOUT high to SDRAM data invalid
Symbol
2.7
—
1/CLKOUT
t_CHDAV
t_CHDCV
t_CHDAI
t_CHDCI
t_DDVCH
t_CHDDI
t_CHDDVW
t_CHDDIW
MIn
Max
Unit
3.6
V
CLKOUT MHz
—
ns
2
-
11.1
ns
11.1
ns
1.0
-
ns
1.0
-
ns
7.3
-
ns
1.0
-
ns
-
11.1
ns
1.0
-
ns
1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
2. CLKOUT is same as FB_CLK, maximum frequency can be 75 MHz
3. D7 and D8 are for write cycles only.
Following figure shows an SDRAM write cycle.
Kinetis K80 Sub-Family, Rev.4, 09/2015.
45
Freescale Semiconductor, Inc.