UJA1065 Datasheet, PDF (62/76 Pages) NXP Semiconductors – High-speed CAN/LIN fail-safe system basis chip

NXP Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
10. Dynamic characteristics
Table 27. Dynamic characteristics
T_vj = −40 °C to +150 °C; V_BAT42 = 5.5 V to 52 V; V_BAT14 = 5.5 V to 27 V; V_BAT42 ≥ V_BAT14 − 1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.^[1]
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see Figure 24)^[2]
T_cyc
clock cycle time
t_lead
enable lead time
960
-
-
ns
clock is LOW when SPI select
240
-
-
ns
falls
t_lag
enable lag time
clock is LOW when SPI select
240
-
-
ns
rises
t_SCKH
clock HIGH time
t_SCKL
clock LOW time
t_su
input data setup time
t_h
input data hold time
t_DOV
output data valid time
pin SDO; C_L = 10 pF
t_SSH
SPI select HIGH time
CAN transceiver timing; pins CANL, CANH, TXDC and RXDC
480
-
-
ns
480
-
-
ns
80
-
-
ns
400
-
-
ns
-
-
400
ns
480
-
-
ns
t_t(reces-dom) output transition time
10 % to 90 %; C = 100 pF;
-
100 -
ns
recessive to dominant
R = 60 Ω; see Figure 25 and
Figure 26
t_t(dom-reces) output transition time
90 % to 10 %; C = 100 pF;
-
100 -
ns
dominant to recessive
R = 60 Ω; see Figure 25 and
Figure 26
t_PHL
propagation delay TXDC to 50 % V_TXDC to 50 % V_RXDC;
70
120 220
ns
RXDC (HIGH-to-LOW
C = 100 pF; R = 60 Ω; see
transition)
Figure 25 and Figure 26
t_PLH
propagation delay TXDC to 50 % V_TXDC to 50 % V_RXDC;
70
120 220
ns
RXDC (LOW-to-HIGH
C = 100 pF; R = 60 Ω; see
transition)
Figure 25 and Figure 26
t_TXDC(dom)
TXDC permanent dominant Active mode, On-line mode or
1.5
-
6
ms
disable time
On-line Listen mode;
V_V2 = 5 V; V_TXDC = 0 V
t_CANH(dom1),
t_CANL(dom1)
minimum dominant time first Off-line mode
pulse for wake-up on pins
CANH and CANL
3
-
-
μs
t_CANH(reces),
t_CANL(reces)
minimum recessive time
pulse (after first dominant)
for wake-up on pins CANH
and CANL
Off-line mode
1
-
-
μs
t_CANH(dom2),
t_CANL(dom2)
minimum dominant time
Off-line mode
second pulse for wake-up on
pins CANH, CANL
1
-
-
μs
t_timeout
time-out period between
wake-up message and
confirm message
On-line Listen mode
115
-
285
ms
UJA1065_7
Product data sheet
Rev. 07 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
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