UJA1065 Datasheet, PDF (31/76 Pages) NXP Semiconductors – High-speed CAN/LIN fail-safe system basis chip

NXP Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Table 6.
Bit
11 to 6
Mode register bit description (bits 11 to 6)^[1]
Symbol
Description
Value
NWP[5:0]
Nominal
00 1001
Watchdog Period _{00 1100}
WDPRE = 00 (as
set in the Special
01 0010
Mode register) ^{01 0100}
01 1011
10 0100
10 1101
11 0011
11 0101
11 0110
Nominal
00 1001
Watchdog Period _{00 1100}
WDPRE = 01 (as
set in the Special
01 0010
Mode register) ^{01 0100}
01 1011
10 0100
10 1101
11 0011
11 0101
11 0110
Nominal
00 1001
Watchdog Period _{00 1100}
WDPRE = 10 (as _{01 0010}
set in the Special
Mode register) ^{01 0100}
01 1011
10 0100
10 1101
11 0011
11 0101
11 0110
Time
Normal
mode (ms)
4
8
16
32
40
48
56
64
72
80
6
12
24
48
60
72
84
96
108
120
10
20
40
80
100
120
140
160
180
200
Standby
mode (ms)
20
40
80
160
320
640
1024
2048
4096
OFF^[2]
30
60
120
240
480
960
1536
3072
6144
OFF^[2]
50
100
200
400
800
1600
1560
5120
10240
OFF^[2]
Flash mode
(ms)
20
40
80
160
320
640
1024
2048
4096
8192
30
60
120
240
480
960
1536
3072
6144
12288
50
100
200
400
800
1600
1560
5120
10240
20480
Sleep mode
(ms)
160
320
640
1024
2048
3072
4096
6144
8192
OFF^[3]
240
480
960
1536
3072
4608
6144
9216
12288
OFF^[3]
400
800
1600
2560
5120
7680
10240
15360
20480
OFF^[3]
UJA1065_7
Product data sheet
Rev. 07 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
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