LPC2927_10 Datasheet, PDF (60/95 Pages) NXP Semiconductors – ARM9 microcontroller with CAN, LIN, and USB

NXP Semiconductors
LPC2927/2929
ARM9 microcontroller with CAN, LIN, and USB
6.17.1 Functional description
The Vectored Interrupt Controller routes incoming interrupt requests to the ARM
processor. The interrupt target is configured for each interrupt request input of the VIC.
The targets are defined as follows:
• Target 0 is ARM processor FIQ (fast interrupt service).
• Target 1 is ARM processor IRQ (standard interrupt service).
Interrupt-request masking is performed individually per interrupt target by comparing the
priority level assigned to a specific interrupt request with a target-specific priority
threshold. The priority levels are defined as follows:
• Priority level 0 corresponds to ‘masked’ (i.e. interrupt requests with priority 0 never
lead to an interrupt).
• Priority 1 corresponds to the lowest priority.
• Priority 15 corresponds to the highest priority.
Software interrupt support is provided and can be supplied for:
• Testing RTOS (Real-Time Operating System) interrupt handling without using
device-specific interrupt service routines.
• Software emulation of an interrupt-requesting device, including interrupts.
6.17.2 Clock description
The VIC is clocked by CLK_SYS_VIC, see Section 6.7.2.
LPC2927_29_4
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 14 April 2010
© NXP B.V. 2010. All rights reserved.
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