PSMN9R0-30YL_10 Datasheet, PDF (6/14 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PSMN9R0-30YL
N-channel TrenchMOS logic level FET
Table 6. Characteristics …continued
Symbol Parameter
Conditions
Min Typ Max Unit
Source-drain diode
V_SD
source-drain voltage I_S = 25 A; V_GS = 0 V; T_j = 25 °C; see Figure 17 -
0.88 1.2 V
t_rr
reverse recovery time I_S = 20 A; dI_S/dt = -100 A/µs; V_GS = 0 V;
Q_r
recovered charge
V_DS = 20 V
-
26
-
ns
-
16
-
nC
[1] Tested to JEDEC standards where applicable.
80
I_D
(A)
10
4.5
60
3.5
003aac534
40
V_GS (V) = 3
2.8
20
2.6
2.4
2.2
0
0
2
4
6
8
10
V_DS (V)
003aac535
60
I_D
(A)
40
20
0
0
T_j = 150 °C
1
2
25 °C
3 _{VGS (V)} 4
Fig 5. Output characteristics: drain current as a
Fig 6. Transfer characteristics: drain current as a
function of drain-source voltage; typical values
function of gate-source voltage; typical values
003aac539
60
14
003aac546
R_DSon
g_fs
(mΩ)
V_GS (V) = 3.5
(S)
12
50
10
4.5
8
40
7.5
10
6
30
5
10
15
20
25
30
I_D (A)
4
0
20
40 I_D (A) 60
Fig 7. Forward transconductance as a function of
drain current; typical values
Fig 8. Drain-source on-state resistance as a function
of drain current; typical values
PSMN9R0-30YL_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 5 January 2010
© NXP B.V. 2010. All rights reserved.
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