74ABT652A Datasheet, PDF (6/19 Pages) NXP Semiconductors – Octal transceiver/register, non-inverting 3-State

NXP Semiconductors
74ABT652A
Octal transceiver/register; non-inverting; 3-state
6. Functional description
6.1 Function table
Table 3.
Inputs
OEAB
L
L
X
Function table ^[1]
OEBA
H
H
H
CPAB
H or L
↑
↑
CPBA
H or L
↑
H or L
SAB
X
X
X
H
H
↑
↑
[3]
L
X
H or L ↑
X
L
L
↑
↑
X
L
L
X
X
X
L
L
X
H or L X
H
H
X
X
L
H
H
H or L X
H
H
L
H or L H or L H
SBA
X
X
X
X
X
[3]
L
H
X
X
H
Data I/O
An
input
input
input
input
unspecified
output ^[2]
unspecified
output ^[2]
output
output
input
input
output
Bn
input
input
unspecified
output ^[2]
unspecified
output ^[2]
input
input
input
input
output
output
output
Operating mode
isolation
store A and B data
store A, hold B
store A in both registers
hold A, store B
store B in both registers
real time B data to A bus
stored B data to A bus
real time A data to B bus
store A data to B bus
stored A data to B bus;
stored B data to A bus
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH clock transition.
[2] The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock.
[3] If both select controls (SAB and SBA) are LOW, then clocks can occur simultaneously. If either select control is HIGH, the clocks must
be staggered in order to load both registers.
Figure 3 demonstrates the four fundamental bus-management functions that can be
performed with the 74ABT652A.
The select pins determine whether data is stored or transferred through the device in real
time.
The output enable pins determine the direction of the data flow.
74ABT652A_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 12 March 2010
© NXP B.V. 2010. All rights reserved.
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