P89LPC932A1 Datasheet, PDF (54/64 Pages) NXP Semiconductors – 8-Bit Microcontroller with accelerated two-clock 80C51 core 8kB 3V byte-erasable flash with 512-byte data EEPROM

NXP Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
SS
SPICLK
(CPOL = 0)
(input)
SPICLK
(CPOL = 1)
(input)
t_SPIA
MISO
(output)
t_SPIR
t_SPILEAD
T_SPICYC
t_SPIF
t_SPICLKH
t_SPICLKL
t_SPIR
t_SPIF
t_SPICLKL
t_SPIR
t_SPICLKH
t_SPIOH
t_SPIDV
not defined
t_SPIOH
t_SPIDV
slave MSB/LSB out
t_SPIOH
t_SPIDV
t_SPILAG
t_SPIR
slave LSB/MSB out
t_SPIDIS
MOSI
(input)
t_SPIDSU t_SPIDH
MSB/LSB in
Fig 27. SPI slave timing (CPHA = 1)
t_SPIDSU
t_SPIDSU t_SPIDH
LSB/MSB in
002aaa911
10.2 ISP entry mode
Table 11. Dynamic characteristics, ISP entry mode
V_DD = 2.4 V to 3.6 V, unless otherwise specified.
T_amb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
t_VR
V_DD active to RST active delay time
t_RH
RST HIGH time
t_RL
RST LOW time
50
-
-
1
-
32
1
-
-
Unit
µs
µs
µs
V_DD
RST
Fig 28. ISP entry waveform
t_VR
t_RH
t_RL
002aaa912
P89LPC932A1_3
Product data sheet
Rev. 03 — 12 March 2007
© NXP B.V. 2007. All rights reserved.
54 of 64