GTL2003 Datasheet, PDF (5/19 Pages) NXP Semiconductors – 8-bit bidirectional low voltage translator

NXP Semiconductors
GTL2003
8-bit bidirectional low voltage translator
8. Application design-in information
8.1 Bidirectional translation
For the bidirectional clamping configuration, higher voltage to lower voltage or lower
voltage to higher voltage, the GREF input must be connected to DREF and both pins
pulled to HIGH side V_CC through a pull-up resistor (typically 200 kΩ). A filter capacitor on
DREF is recommended. The processor output can be totem pole or open-drain (pull-up
resistors may be required) and the chip set output can be totem pole or open-drain
(pull-up resistors are required to pull the Dn outputs to V_CC). However, if either output is
totem pole, data must be unidirectional or the outputs must be 3-stateable and the outputs
must be controlled by some direction control mechanism to prevent HIGH-to-LOW
contentions in either direction. If both outputs are open-drain, no direction control is
needed. The opposite side of the reference transistor (SREF) is connected to the
processor core power supply voltage. When DREF is connected through a 200 kΩ resistor
to a 3.3 V to 5.5 V V_CC supply and SREF is set between 1.0 V to (V_CC − 1.5 V), the output
of each Sn has a maximum output voltage equal to SREF and the output of each Dn has
a maximum output voltage equal to V_CC.
1.8 V
1.5 V
1.2 V
1.0 V
V_CORE
CPU I/O
200 kΩ
GTL2002
GND
SREF
S1
S2
GREF
DREF
D1
D2
5V
totem pole or
open-drain I/O
V_CC
CHIPSET I/O
increase bit size
by using 8-bit GTL2003,
10-bit GTL2010,
or 22-bit GTL2000
S3
D3
S4
D4
S5
D5
Sn
Dn
3.3 V
V_CC
CHIPSET I/O
002aac642
Typical bidirectional voltage translation.
Fig 4. Bidirectional translation to multiple higher voltage levels such as an I²C-bus
application
GTL2003_1
Product data sheet
Rev. 01 — 27 July 2007
© NXP B.V. 2007. All rights reserved.
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