SC16C852V Datasheet, PDF (44/54 Pages) NXP Semiconductors – Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
RXA, RXB
start
bit
data bits (0 to 7)
parity stop
bit bit
D0 D1 D2 D3 D4 D5 D6 D7
first byte that
reaches the
trigger level
RXRDYA
RXRDYB
IOR
Fig 16. Receive ready timing in FIFO mode
t_{d(stop-RXRDY)}
active data
ready
t_{d(IOR-RXRDYH)}
active
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TXA, TXB
INTA, INTB
IOW
start
bit
data bits (0 to 7)
next
data
parity stop start
bit bit bit
D0 D1 D2 D3 D4 D5 D6 D7
active
5 data bits
6 data bits
7 data bits
t_d(start-INT)
t_d(IOW-TX)
active
transmitter ready
t_d(IOW-INTL)
active
Fig 17. Transmit timing
16 baud rate clock
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SC16C852V_3
Product data sheet
Rev. 03 — 15 October 2007
© NXP B.V. 2007. All rights reserved.
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