SC16C852V Datasheet, PDF (37/54 Pages) NXP Semiconductors – Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.22 Advanced Feature Control Register 2 (AFCR2)
Table 34. Advanced Feature Control Register 2 bits description
Bit Symbol
Description
7:6 AFCR2[7:6] reserved
5
AFCR2[5] RTSInvert. Invert RTS or DTR signal in auto 9-bit mode.
0 = RTS or DTR is set to 0 by the UART during transmission, and to 1
during reception
1 = RTS or DTR is set to 1 by the UART during transmission, and to 0
during reception
4
AFCR2[4] RTSCon. Enable the transmitter to control RTS or DTR signal in auto 9-bit
mode.
0 = transmitter does not control RTS or DTR signal
1 = transmitter controls RTS or DTR signal
3
AFCR2[3] RS485 RTS/DTR. Select RTSA/RTSB or DTRA/DTRB pin to control the
external transceiver.
0 = RTSA/RTSB pin is used to control the external transceiver
1 = DTRA/DTRB pin is used to control the external transceiver
2
AFCR2[2] TXDisable. Disable transmitter.
0 = transmitter is enabled
1 = transmitter is disabled
1
AFCR2[1] RXDisable. Disable receiver.
0 = receiver is enabled
1 = receiver is disabled
0
AFCR2[0] 9-bitMode. Enable 9-bit mode or Multidrop (RS-485) mode.
0 = normal RS-232 mode
1 = enable 9-bit mode
SC16C852V_3
Product data sheet
Rev. 03 — 15 October 2007
© NXP B.V. 2007. All rights reserved.
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