SC16C852V Datasheet, PDF (40/54 Pages) NXP Semiconductors – Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
10. Dynamic characteristics
Table 39. Dynamic characteristics
T_amb = −40 °C to +85 °C; V_DD = 1.65 V to 1.95 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
f_XTAL
oscillator/clock frequency
[1] _-
-
t_d(CS-LLA)
delay time from CS to LLA
10
-
t_su(A-LLAL)
setup time from address to LLA LOW
5
-
t_w(LLA)
t_h(LLAH-A)
LLA pulse width time
address hold time after LLA HIGH
10
-
10
-
t_d(IOW)
t_d(IOR-DV)
IOW delay time
delay time from IOR to data valid
10
-
25 pF load
-
-
t_w(IOR)
IOR pulse width time
20
-
t_d(LLAH-IORL) delay time from LLA HIGH to IOR LOW
10
-
t_w(IOW)
IOW pulse width time
10
-
t_h(IOWH-D)
data input hold time after IOW HIGH
5
-
t_d(LLAH-IOWL) delay time from LLA HIGH to IOW LOW
10
-
t_su(D-IOWH)
t_d(IOR)
data setup time from data input to IOW HIGH
IOR delay time
5
-
10
-
t_dis(IOR-QZ)
disable time from IOR to high-impedance data 25 pF load
-
-
output^[3]
t_d(IOW-Q)
t_d(modem-INT)
delay time from IOW to data output
delay time from modem to INT
25 pF load
-
-
25 pF load
-
-
t_d(IOR-INTL)
delay time from IOR to INT LOW
25 pF load
-
-
t_WH
pulse width HIGH
6
-
t_WL
pulse width LOW
6
-
t_w(clk)
t_d(stop-INT)
t_{d(stop-RXRDY)}
clock pulse width
delay time from stop to INT
delay time from stop to RXRDY
12.5
-
25 pF load ^[2] -
-
25 pF load ^[2] -
-
t_{d(IOR-RXRDYH)} delay time from IOR to RXRDY HIGH
25 pF load
-
-
t_d(start-INT)
t_d(IOW-TX)
delay time from start to INT
delay time from IOW to TX
25 pF load
-
-
[2] _{8TRCLK -}
t_d(IOW-INTL)
delay time from IOW to INT LOW
25 pF load
-
-
t_{d(IOW-TXRDYH)} delay time from IOW to TXRDY HIGH
t_{d(start-TXRDY)} delay time from start to TXRDY
25 pF load
-
-
25 pF load ^[2] -
-
t_{w(RESET_N)}
pulse width on pin RESET
10
-
[1] External clock only; maximum crystal frequency is 24 MHz.
[2] RCLK is an internal frequency and it is equal to 16 times the baud rate.
[3] 10 % of the data bus fall or rise time.
Max
Unit
80
MHz
-
ns
-
ns
-
ns
-
ns
-
ns
15
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
15
ns
50
ns
50
ns
50
ns
-
ns
-
ns
-
ns
1T_RCLK s
1T_RCLK s
50
ns
1T_RCLK s
24T_RCLK s
50
ns
50
ns
8T_RCLK s
-
ns
SC16C852V_3
Product data sheet
Rev. 03 — 15 October 2007
© NXP B.V. 2007. All rights reserved.
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