PRTR5V0U8S Datasheet, PDF (4/7 Pages) NXP Semiconductors – Integrated octal low-capacity ESD protection to IEC 61000-4-2 level 4

NXP Semiconductors
PRTR5V0U8S
Integrated octal low-capacity ESD protection
7. Package outline
TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm
SOT552-1
D
c
y
Z
10
6
E
A
X
HE
vM A
pin 1 index
1
e
5
bp
wM
A2 _A1
(A3)
A
θ
Lp
L
detail X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D⁽¹⁾ E⁽²⁾ e
HE
L
Lp
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.15
0.23
0.15
3.1
2.9
3.1
2.9
0.5
5.0
4.8
0.95
0.7
0.4
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT552-1
v
w
y
Z ⁽¹⁾
θ
0.1
0.1
0.1
0.67
0.34
6°
0°
EUROPEAN
PROJECTION
ISSUE DATE
99-07-29
03-02-18
Fig 1. Package outline SOT552-1 (TSSOP10)
PRTR5V0U8S_1
Preliminary data sheet
Rev. 01 — 14 January 2008
© NXP B.V. 2008. All rights reserved.
4 of 7