ADC1410S065 Datasheet, PDF (31/35 Pages) NXP Semiconductors – Single 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
Table 30. LVDS DDR output register 2 (address 0022h) bit description …continued
Bit Symbol
Access Value Description
2 to 0 LVDS_INTTER R/W
internal termination for LVDS buffer (DAV and DATA)
000
no internal termination
001
300 Ω
010
180 Ω
011
110 Ω
100
150 Ω
101
100 Ω
110
81 Ω
111
60 Ω
11.7.4 Serial timing interface
SPI timing is shown in Figure 31.
t_su
CS
t_su
t_h
t_w(SCLK)
t_w(SCLKL)
t_w(SCLKH)
t_h
SCLK
SDIO
R/W W1 W0 A12
A11
Fig 31. SPI timing
SPI timing characteristics are detailed in Table 9.
D2
D1
D0
005aaa065
ADC1410S065_080_105_125_2
Objective data sheet
Rev. 02 — 4 June 2009
© NXP B.V. 2009. All rights reserved.
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