ADC1410S065 Datasheet, PDF (1/35 Pages) NXP Semiconductors – Single 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs

ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
CMOS or LVDS DDR digital outputs
Rev. 02 — 4 June 2009
Objective data sheet
1. General description
The ADC1410S is a single channel 14-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1410S is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,
thanks to a separate digital output supply. It supports the LVDS (Low Voltage Differential
Signalling) DDR (Double Data Rate) output standard. An integrated SPI (Serial Peripheral
Interface) allows the user to easily configure the ADC. The device also includes a
programmable gain amplifier with a flexible input voltage range. With excellent dynamic
performance from the baseband to input frequencies of 170 MHz or more, the ADC1410S
is ideal for use in communications, imaging and medical applications.
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1.5
1.5
1
1
0.5
0.5
0
0
-0.5
-0.5
-1
-1
-1.5
0
4000
8000
12000
16000
-1.5
0
4000
8000
12000
16000
Fig 1. Integral Non-Linearity (INL) Fig 2. Differential Non-Linearity
(DNL)
2. Features
0
dB
-40
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-80
-120
0
10
20
30
40
f (MHz)
Fig 3. Output spectrum: −1 dBFS,
80 Msps, f_i = 4.43 MHz
I SNR, 73 dB
I SFDR, 90 dBc
I Sample rate up to 125 Msps
I 14-bit pipelined ADC core
I Single 3 V supply
I Flexible input voltage range: 1 V to 2 V
p-p with 6 dB programmable fine gain
I CMOS or LVDS DDR digital outputs
I INL ±1 LSB, DNL ±0.5 LSB (typical)
I Input bandwidth, 600 MHz
I Power dissipation, 387 at 80 Msps
I SPI Interface
I Duty cycle stabilizer
I Fast OTR detection
I Offset binary, 2’s complement, gray
code
I Power-down and Sleep modes
I HVQFN40 package