ADC1410S065 Datasheet, PDF (21/35 Pages) NXP Semiconductors – Single 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
3.5 mA
typ
VCCO
−
+
D_nP/D_{n + 1}P
D_nM/D_{n + 1}M
+
−
100 Ω RECEIVER
OGND
005aaa058
Fig 24. LVDS DDR digital output buffer - externally terminated
Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver
side (Figure 24) or internally via SPI control bits LVDS_INTTER (see Figure 25 and
Table 30).
3.5 mA
typ
VCCO
−
+
D_xP/Dx _{+ 1}P
100 Ω _{DxM/Dx + 1M}
+
−
OGND
RECEIVER
Fig 25. LVDS DDR digital output buffer - internally terminated
005aaa059
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI and DATAI; see Table 29) in order to adjust the output logic voltage
levels.
11.5.3 Data valid (DAV) output clock
A data valid output clock signal (DAV) is provided that can be used to capture the data
delivered by the ADC1410S. Detailed timing diagrams for CMOS and LVDS DDR modes
are provided in Figure 26 and Figure 27 respectively.
11.5.4 Out-of-Range (OTR)
An out-of-range signal is provided on pin OTR. By default, pin OTR goes HIGH fourteen
clock cycles after an OTR event has occurred. The OTR response can be speeded up by
enabling Fast OTR (bit FASTOTR = 1; see Table 27). When Fast OTR is enabled, OTR
goes HIGH four clock cycles after the OTR event. The Fast OTR detection threshold
(below full scale) can be programmed via bits FASTOTR_DET.
ADC1410S065_080_105_125_2
Objective data sheet
Rev. 02 — 4 June 2009
© NXP B.V. 2009. All rights reserved.
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