SSTUB32866_10 Datasheet, PDF (3/30 Pages) NXP Semiconductors – 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

NXP Semiconductors
5. Functional diagram
SSTUB32866
1.8 V DDR2-800 configurable registered buffer with parity
RESET
CK
CK
VREF
DCKE
DODT
DCS
CSR
SSTUB32866
1D
C1
R
1D
C1
R
1D
C1
R
QCKEA
QCKEB⁽¹⁾
QODTA
QODTB⁽¹⁾
QCSA
QCSB⁽¹⁾
D2
0
1
1D
C1
R
Q2A
Q2B⁽¹⁾
to 10 other channels
(D3, D5, D6, D8 to D14)
002aac010
(1) Disabled in 1 : 1 configuration.
Fig 1. Functional diagram of SSTUB32866; 1 : 2 Register A configuration with C0 = 0
and C1 = 1 (positive logic)
SSTUB32866_4
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 15 April 2010
© NXP B.V. 2010. All rights reserved.
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