SSTUB32866_10 Datasheet, PDF (19/30 Pages) NXP Semiconductors – 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

NXP Semiconductors
SSTUB32866
1.8 V DDR2-800 configurable registered buffer with parity
11.2 Data output slew rate measurement information
V_DD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z_o = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
DUT
V_DD
R_L = 50 Ω
OUT
C_L = 10 pF⁽¹⁾
test point
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(1) C_L includes probe and jig capacitance.
Fig 16. Load circuit, HIGH-to-LOW slew measurement
output
dv_f
80 %
20 %
dt_f
V_OH
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Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT
C_L = 10 pF⁽¹⁾
test point
R_L = 50 Ω
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(1) C_L includes probe and jig capacitance.
Fig 18. Load circuit, LOW-to-HIGH slew measurement
dv_r
output
dt_r
80 %
20 %
V_OH
V_OL
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Fig 19. Voltage waveforms, LOW-to-HIGH slew rate measurement
SSTUB32866_4
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 15 April 2010
© NXP B.V. 2010. All rights reserved.
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