SSTUB32866_10 Datasheet, PDF (13/30 Pages) NXP Semiconductors – 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

NXP Semiconductors
SSTUB32866
1.8 V DDR2-800 configurable registered buffer with parity
Table 9. Timing requirements
At recommended operating conditions (see Table 7), unless otherwise specified. See Section 11.1.
Symbol Parameter
Conditions
Min Typ
f_clock
t_W
t_ACT
t_INACT
t_su
clock frequency
pulse width
CK, CK HIGH or LOW
differential inputs active time
differential inputs inactive time
set-up time
DCS before CK↑, CK↓, CSR HIGH;
CSR before CK↑, CK↓, DCS HIGH
-
-
1
-
[1][2] _-
-
[1][3] _-
-
0.6 -
DCS before CK↑, CK↓, CSR LOW
0.5 -
DODT, DCKE and data (Dn) before CK↑,
CK↓
0.5 -
PAR_IN before CK↑, CK↓
0.5 -
t_h
hold time
DCS, DODT, DCKE and data (Dn) after
CK↑, CK↓
0.4 -
PAR_IN after CK↑, CK↓
0.4 -
Max Unit
450 MHz
-
ns
10 ns
15 ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
[1] This parameter is not necessarily production tested.
[2] VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of t_ACT(max) after RESET is taken
HIGH.
[3] VREF, data and clock inputs must be held at valid levels (not floating) a minimum time of t_INACT(max) after RESET is taken LOW.
Table 10. Switching characteristics
At recommended operating conditions (see Table 7), unless otherwise specified. See Section 11.1.
Symbol Parameter
Conditions
Min Typ
f_max
t_PDM
maximum input clock frequency
peak propagation delay
single bit switching;
from CK↑ and CK↓ to Qn
450 -
[1] _1.1
-
t_PD
t_LH
t_HL
t_PDMSS
propagation delay
LOW to HIGH delay
HIGH to LOW delay
simultaneous switching peak
propagation delay
from CK↑ and CK↓ to PPO
from CK↑ and CK↓ to QERR
from CK↑ and CK↓ to QERR
from CK↑ and CK↓ to Qn
0.5 -
1.2 -
1
-
[1][2] _-
-
t_PHL
HIGH to LOW propagation delay
from RESET↓ to Qn↓
from RESET↓ to PPO↓
-
-
-
-
t_PLH
LOW to HIGH propagation delay
from RESET↓ to QERR↑
-
-
[1] Includes 350 ps of test load transmission line delay.
[2] This parameter is not necessarily production tested.
Max Unit
-
MHz
1.5 ns
1.7 ns
3
ns
2.4 ns
1.6 ns
3
ns
3
ns
3
ns
Table 11. Data output edge rates
At recommended operating conditions (see Table 7), unless otherwise specified. See Section 11.2.
Symbol Parameter
Conditions
Min Typ
dV/dt_r
rising edge slew rate
from 20 % to 80 %
1
-
dV/dt_f
falling edge slew rate
from 80 % to 20 %
1
-
dV/dt_Δ
absolute difference between dV/dt_r from 20 % or 80 %
and dV/dt_f
to 80 % or 20 %
-
-
Max Unit
4
V/ns
4
V/ns
1
V/ns
SSTUB32866_4
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 15 April 2010
© NXP B.V. 2010. All rights reserved.
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