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PTN3361B Datasheet, PDF (3/29 Pages) NXP Semiconductors – HDMI/DVI level shifter with dongle detect support and active DDC buffer
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
2. Features
2.1 High-speed TMDS level shifting
I Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.3a compliant open-drain current-steering differential output signals
I Pin-programmable pre-emphasis feature
I TMDS level shifting operation up to 1.65 Gbit/s per lane (165 MHz character clock)
I TMDS level shifting operation up to 2.25 Gbit/s per lane (225 MHz character clock)
using pre-emphasis feature
I Integrated 50 Ω termination resistors for self-biasing differential inputs
I Back-current safe outputs to disallow current when device power is off and monitor is
on
I Disable feature to turn off TMDS inputs and outputs and to enter low-power state
2.2 DDC level shifting
I Integrated active DDC buffering and level shifting (3.3 V source to 5 V sink side)
I Rise time accelerator on sink-side DDC ports
I 0 Hz to 400 kHz I2C-bus clock frequency
I Back-power safe sink-side terminals to disallow backdrive current when power is off or
when DDC is not enabled
2.3 HDMI dongle detect support
I Incorporates I2C slave ROM
I Responds to DDC read to address 81h with predetermined byte sequence
I Feature enabled by pin DDET (must be enabled for correct operation in accordance
with DisplayPort interoperability guideline
2.4 HPD level shifting
I HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or
from 5 V on the sink side to 3.3 V on the source side
I Integrated 200 kΩ pull-down resistor on HPD sink input guarantees ‘input LOW’ when
no display is plugged in
I Back-power safe design on HPD_SINK to disallow backdrive current when power is off
2.5 General
I Power supply 3.3 V ± 10 %
I ESD resilience to 7 kV HBM, 1 kV CDM
I Support for optional HDMI dongle detection via DDC/I2C-bus channel
I Power-saving modes (using output enable)
I Back-current-safe design on all sink-side main link, DDC and HPD terminals
I Transparent operation: no re-timing or software configuration required
PTN3361B_2
Product data sheet
Rev. 02 — 7 October 2009
© NXP B.V. 2009. All rights reserved.
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