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| PSMN005-75P Datasheet, PDF (3/13 Pages) NXP Semiconductors – N-channel logic level field-effect power transistor in a plastic package using TrenchMOS technology. | |||
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NXP Semiconductors
PSMN005-75P
N-channel TrenchMOS SiliconMAX standard level FET
4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDS
drain-source voltage
Tj ⥠25 °C; Tj ⤠175 °C
VDGR
drain-gate voltage
Tj ⤠175 °C; Tj ⥠25 °C; RGS = 20 kâ¦
VGS
gate-source voltage
ID
drain current
VGS = 10 V; Tmb = 100 °C; see Figure 1
VGS = 10 V; Tmb = 25 °C; see Figure 1 and 3
IDM
peak drain current
tp ⤠10 µs; pulsed; Tmb = 25 °C; see Figure 3
Ptot
total power dissipation Tmb = 25 °C; see Figure 2
Tstg
storage temperature
Tj
junction temperature
VGSM
peak gate-source voltage pulsed; tp ⤠50 µs; δ 25 %; Tj ⤠150 °C
Source-drain diode
IS
source current
ISM
peak source current
Avalanche ruggedness
Tmb = 25 °C
tp ⤠10 µs; pulsed; Tmb = 25 °C
EDS(AL)S
non-repetitive
drain-source avalanche
energy
VGS = 10 V; Tj(init) = 25 °C; ID = 75 A; Vsup = 15 V;
unclamped; tp = 0.1 ms; RGS = 50 â¦
IDS(AL)S
non-repetitive
drain-source avalanche
current
VGS = 10 V; Vsup = 15 V; RGS = 50 â¦;
Tj(init) = 25 °C; unclamped
Min Max Unit
-
75
V
-
75
V
-20 20
V
-
75
A
-
75
A
-
400 A
-
230 W
-55 175 °C
-55 175 °C
-30 30
V
-
75
A
-
400 A
-
500 mJ
-
75
A
120
03ah89
120
03aa16
Ider
Pder
(%)
(%)
80
80
40
40
0
0
50
100
150
200
Tmb (°C)
0
0
50
100
150
200
Tmb (°C)
Fig 1. Normalized continuous drain current as a
function of mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
PSMN005-75P_1
Product data sheet
Rev. 01 â 17 November 2009
© NXP B.V. 2009. All rights reserved.
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