GTL2008 Datasheet, PDF (3/22 Pages) NXP Semiconductors – 12-bit GTL to LVTTL translator with power good control and high-impedance LVTTL and GTL outputs

NXP Semiconductors
GTL2008
GTL translator with power good control and high-impedance outputs
5. Functional diagram
GTL VREF
1AO
LVTTL outputs
(open-drain)
2AO
5A
LVTTL inputs/outputs
(open-drain)
6A
LVTTL input EN1
GTL input 11BI
GTL2008
1
2
3
4
5
6
7
LVTTL input/output
(open-drain)
11A
8
GTL input 9BI
9
3AO
10
LVTTL outputs
(open-drain)
4AO
11
27
1BI
GTL inputs
26
2BI
&
25
&
24
23
(2)
1
22
DELAY⁽¹⁾
21
DELAY⁽¹⁾
20
19
7BO1
7BO2
GTL outputs
EN2 LVTTL input
11BO GTL output
5BI
6BI
GTL inputs
3BI
18
4BI
10AI1
12
LVTTL inputs
10AI2
13
1
17
10BO1
1
GTL outputs
16
10BO2
15
9AO LVTTL output
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(1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the
LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the 7BO1/7BO2 outputs.
(2) The 11BO output is driven LOW after V_CC is powered up with EN2 LOW to prevent reporting of a fault condition before EN2
goes HIGH.
Fig 1. Logic diagram of GTL2008
GTL2008_4
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 19 February 2010
© NXP B.V. 2010. All rights reserved.
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