SC16C850SV Datasheet, PDF (28/46 Pages) NXP Semiconductors – 1.8 V single UART, 20 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface

NXP Semiconductors
SC16C850SV
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.9 Extra Feature Control Register (EFCR)
This is a write-only register, and it allows the software access to these registers:
First Extra Register Set, Second Extra Register Set, Transmit FIFO Level Counter
(TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT).
Table 22. Extra Feature Control Register bits description
Bit Symbol Description
7:3 EFCR[7:3] reserved
2:1 EFCR[2:1] Enable Extra Feature Control bits
00 = General Register Set is accessible
01 = First Extra Register Set is accessible
10 = Second Extra Register Set is accessible
11 = reserved
0
EFCR[0] Enable TXLVLCNT and RXLVLCNT access
0 = TXLVLCNT and RXLVLCNT are disabled
1 = TXLVLCNT and RXLVLCNT are enabled and can be read
Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can
only be accessed if EFCR[2:1] are zeroes.
7.10 Scratchpad Register (SPR)
The SC16C850SV provides a temporary data register to store 8 bits of user information.
7.11 Division Latch (DLL and DLM)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLM stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
7.12 Transmit FIFO Level Count (TXLVLCNT)
This register is a read-only register. It reports the number of spaces available in the
transmit FIFO.
7.13 Receive FIFO Level Count (RXLVLCNT)
This register is a read-only register. It reports the fill level of the receive FIFO (the number
of characters in the RXFIFO).
SC16C850SV_1
Product data sheet
Rev. 01 — 8 July 2008
© NXP B.V. 2008. All rights reserved.
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