SC16C850SV Datasheet, PDF (27/46 Pages) NXP Semiconductors – 1.8 V single UART, 20 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface

NXP Semiconductors
SC16C850SV
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Table 20. Line Status Register bits description …continued
Bit Symbol Description
0 LSR[0] Receive data ready.
logic 0 = no data in Receive Holding Register or FIFO (normal default condition)
logic 1 = data has been received and is saved in the Receive Holding Register
or FIFO
7.8 Modem Status Register (MSR)
This register shares the same address as EFCR register. This is a read-only register and
it provides the current state of the control interface signals from the modem, or other
peripheral device to which the SC16C850SV is connected. Four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a
control input from the modem changes state. These bits are set to a logic 0 whenever the
CPU reads this register.
When write, the data will be written to EFCR register.
Table 21. Modem Status Register bits description
Bit Symbol Description
7
MSR[7] CD. During normal operation, this bit is the complement of the CD input.
Reading this bit in the loopback mode produces the state of MCR[3] (OP2).
6
MSR[6] RI. During normal operation, this bit is the complement of the RI input. Reading
this bit in the loopback mode produces the state of MCR[2] (OP1).
5
MSR[5] DSR. During normal operation, this bit is the complement of the DSR input.
During the loopback mode, this bit is equivalent to MCR[0] (DTR).
4
MSR[4] CTS. During normal operation, this bit is the complement of the CTS input.
During the loopback mode, this bit is equivalent to MCR[1] (RTS).
3
MSR[3] ∆CD ^[1]
logic 0 = no CD change (normal default condition)
logic 1 = the CD input to the SC16C850SV has changed state since the last
time it was read. A modem Status Interrupt will be generated.
2
MSR[2] ∆RI ^[1]
logic 0 = no RI change (normal default condition)
logic 1 = the RI input to the SC16C850SV has changed from a logic 0 to a
logic 1. A modem Status Interrupt will be generated.
1
MSR[1] ∆DSR ^[1]
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C850SV has changed state since the last
time it was read. A modem Status Interrupt will be generated.
0
MSR[0] ∆CTS ^[1]
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C850SV has changed state since the last
time it was read. A modem Status Interrupt will be generated.
[1] Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.
SC16C850SV_1
Product data sheet
Rev. 01 — 8 July 2008
© NXP B.V. 2008. All rights reserved.
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