SC16C850SV Datasheet, PDF (12/46 Pages) NXP Semiconductors – 1.8 V single UART, 20 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface

NXP Semiconductors
SC16C850SV
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Programming the baud rate generator registers CLKPRES, DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate. The example in Table 6
shows the selectable baud rate table available when using a 1.8432 MHz external clock
input with MCR[7] is 0, SAMPR[1:0] = 00b, and CLKPRES = 0x00.
XTAL1
XTAL2
X1
1.8432 MHz
C1
22 pF
C2
33 pF
Fig 4. Crystal oscillator connection
XTAL1
XTAL2
1.5 kΩ
X1
1.8432 MHz
C1
22 pF
C2
47 pF
002aaa870
f_XTAL1
XTAL1
100 pF
XTAL2
002aac630
Fig 5.
If f_XTAL1 frequency is greater than 50 MHz, then a DC blocking capacitor is required.
XTAL2 pin should be left unconnected when an external clock is used.
External clock connection
Table 6. Baud rate generator programming table using a 1.8432 MHz clock with
MCR[7] = 0, SAMPR[1:0] = 00b, and CLKPRE[3:0] = 0
Output
baud rate
(bit/s)
Output
16× clock divisor
(decimal)
Output
16× clock divisor
(hexadecimal)
DLM
program value
(hexadecimal)
DLL
program value
(hexadecimal)
50
2304
900
09
00
75
1536
600
06
00
110
1047
417
04
17
150
768
300
03
00
300
384
180
01
80
600
192
C0
00
C0
1.2 k
96
60
00
60
2.4 k
48
30
00
30
3.6 k
32
20
00
20
4.8 k
24
18
00
18
7.2 k
16
10
00
10
9.6 k
12
0C
00
0C
19.2 k
6
06
00
06
SC16C850SV_1
Product data sheet
Rev. 01 — 8 July 2008
© NXP B.V. 2008. All rights reserved.
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