ADC1213D065 Datasheet, PDF (28/38 Pages) NXP Semiconductors – Dual 12-bit ADC; 65, 80, 105 or 125 Msps

NXP Semiconductors
ADC1213D065/080/105/125
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 28. SER cfg set-up (address 0803h)
Bit Symbol
Access Value
7 to 4 -
R
0000
3 to 0 CFG_SETUP
R/W
0000
(reset)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to
1101
1110
1111
Description
Not used
Defines quick JEDEC204A configuration. These settings overrule the
CFG_PAD configuration
ADC0: ON; ADC1: ON; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9;
M = 2; L = 2^[1]
ADC0: ON; ADC1: ON; Lane0: ON; Lane1: OFF; F = 4; HD = 0; K = 5;
M = 2; L = 1^[1]
ADC0: ON; ADC1: ON; Lane0: OFF; Lane1: ON; F = 4; HD = 0; K = 5;
M = 2; L = 1 swap line = 1^[1]
ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17;
M = 1; L = 2^[1]
ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17;
M = 1; L = 2; swap adc = 1^[1]
ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9;
M = 1; L = 1^[1]
ADC0: ON; ADC1: OFF; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9;
M = 1; L = 1; swap line = 1^[1]
ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9;
M = 1; L = 1; swap adc = 1^[1]
ADC0: OFF; ADC1: ON; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9;
M = 1; L = 1; swap adc = 1; swap line = 1^[1]
Reserved
ADC0: OFF; ADC1: OFF; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9;
M = 2; L = 2; loop alignment = 1^[1]
ADC0: OFF; ADC1: OFF; Lane0: OFF; Lane1: OFF; F = 2; HD = 0;
K = 9; M = 2; L = 2 → PD^[1]
[1] F : number of byte per frame; HD : High density; K : number of frames per multi frame; M : number of converters; L : number of lanes
See the information about the JESD204A standard on the JEDEC web site.
Table 29. SER control1 (address 0805h)
Bit Symbol
Access Value
Description
7
-
R
0
Not used
6
TRISTATE_CFG_PAD R/W
0
1 (default) CFG pads (3 to 0) are set to high-impedance
5
SYNC_POL
R/W
Defines the synchronization signal polarity:
0 (default) synchronization signal is active high
1
synchronization signal is active low
4
SYNC_SINGLE_ENDED R/W
Defines the input mode of the synchronization signal:
0 (default) synchronization input mode is set in Differential mode
1
synchronization input mode is set in Single-ended mode
3
-
R
1
Not used
2 to 0 RESERVED
-
ADC1213D065_080_105_125_2
Objective data sheet
Rev. 02 — 17 June 2009
© NXP B.V. 2009. All rights reserved.
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