ADC1213D065 Datasheet, PDF (12/38 Pages) NXP Semiconductors – Dual 12-bit ADC; 65, 80, 105 or 125 Msps

NXP Semiconductors
ADC1213D065/080/105/125
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 8. Characteristics …continued
Typical values measured at V_DDA = 3 V, V_DDD = 1.8 V, T_amb = 25 °C and C_L = 5 pF.
Min. and max. values are across the full temperature range T_amb = −40 °C to +85 °C at V_DDA = 3 V, V_DDD = 1.8 V ;
V_i (INAP, INBP) − V_i (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
t_h
hold time
data to SCLKH
CSB to SCLKH
2
-
-
ns
2
-
-
ns
f_clk(max)
maximum clock
frequency
-
-
25
MHz
13. Application information
13.1 Analog inputs
13.1.1 Input stage description
The ADC1213D inputs can be configured as single-ended or differential (selected via SPI
control bit DIFF/SE; see Table 20). Optimal performance is achieved using differential
inputs with the common-mode input voltage, V_I(CM), set to 0.5V_DDA.
The full scale analog input voltage range is configurable between ±1 V (p-p) and
±2 V (p-p) via a programmable internal reference (see Section 13.2 and Table 21 for
further details).
The equivalent circuit of the sample and hold input stage, including ESD protection and
circuit and package parasitics, is shown in Figure 5.
Package
ESD
Parasitics
INAP 1, 14
INBP
INAM 2, 13
INBM
Switch
Ron = 14 Ω _{4 pF}
Sampling
internal Capacitor
clock
Switch
Ron = 14 Ω _{4 pF}
Sampling
internal Capacitor
clock
Fig 5. Input sampling circuit
005aaa069
The sample phase HIGH, because of the NMOS transistors. The voltage is then held on
the sampling capacitors. When the clock signal goes LOW, the stage enters the hold
phase and the voltage information is transmitted to the ADC core.
ADC1213D065_080_105_125_2
Objective data sheet
Rev. 02 — 17 June 2009
© NXP B.V. 2009. All rights reserved.
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