ADC1213D065 Datasheet, PDF (24/38 Pages) NXP Semiconductors – Dual 12-bit ADC; 65, 80, 105 or 125 Msps

NXP Semiconductors
ADC1213D065/080/105/125
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 17. Register allocation map
Addr Register name
Hex
R/W Bit definition
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2 Bit 1
Bit 0
Default
Bin
0003 Channel index R/W
-
-
-
-
-
ADCB ADCA 1111
1111
0005 Reset and
R/W SW_ -
-
-
-
Operating mode
RST
-
PD[1:0]
0000
0000
0006 Clock
R/W -
-
-
SE_SEL DIFF/SE -
CLKDIV2_ DCS_EN 0000
SEL
000X
0008 Vref
R/W -
-
-
-
INTREF_ INTREF[2:0]
EN
0000
0000
0011 Output data
R/W -
-
-
standard
LVDS/ OUTBUF -
CMOS
DATA_FORMAT
000X
0XXX
0013 Offset
R/W -
-
DIG_OFFSET[5:0]
0000
0000
0014 Test pattern 1
R/W -
-
-
-
-
TESTPAT_1[2:0]
0000
0000
0015 Test pattern 2
R/W TESTPAT_2[13:6]
0000
0000
0016 Test pattern 3
R/W TESTPAT_3[5:0]
0000
0000
JESD204A control
0801 Ser_Status
R0
RESERVED[2:0]
0
0
POR_TST PLL_ 0000
INLOCK 0000
0802 Ser_Reset
R/W SW_ 0
0
0
FSM_SW_ ₀
0
RST
RST
0
0000
0000
0803 Ser_Cfg_Setup R/W 0
0
0
0
CFG_SETUP[3:0]
0000 ****
0805 Ser_Control1
R/W 0
TriState SYNC_ SYNC_ 1
_CFG_ POL SINGLE
PAD
ENDED
RESERVED[2:0]
0100
1000
0806 Ser_Control2
R/W 0
0
0
0
0
0
SWAP_ SWAP_ 0000
LANE_1_2 ADC_0_ 00**
1
0808 Ser_Analog_Ctrl R/W 0
0
0
0
0
SWING_SEL[2:0]
0000
01**
0809 Ser_ScramblerA R/W 0
LSB_INIT[6:0]
0000
0000
080A Ser_ScramblerB R/W MSB_INIT[7:0]
1111
1111
080B Ser_PRBS_Ctrl R/W 0
0
0
0
0
0
PRBS_TYPE[1:0] 0000
0000
0820 Cfg_0_DID
R/W*
DID[7:0]
1110
1101
0821 Cfg_1_BID
R/W* 0
0
0
0
BID[3:0]
0000
1010
0822 Cfg_3_SCR_L R/W* SCR 0
0
0
0
0
0
L
*000
000*
0823 Cfg_4_F
R/W* 0
0
0
0
0
F[2:0]
0000
0***
ADC1213D065_080_105_125_2
Objective data sheet
Rev. 02 — 17 June 2009
© NXP B.V. 2009. All rights reserved.
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