SC68C652B Datasheet, PDF (26/43 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, and 68 mode mP interface

NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
7.10 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software flow control selection. When the
Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are
concatenated into two sequential numbers.
Table 23. Enhanced Feature Register bits description
Bit Symbol Description
7
EFR[7] Automatic CTS flow control
logic 0 = automatic CTS flow control is disabled (normal default condition)
logic 1 = enable automatic CTS flow control. Transmission will stop when
CTSn goes to a logic 1. Transmission will resume when the CTSn pin returns
to a logic 0.
6
EFR[6] Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be
generated when the receive FIFO is filled to the programmed trigger level and
RTSn will go to a logic 1 at the next trigger level. RTSn will return to a logic 0
when data is unloaded below the next lower trigger level (programmed trigger
level 1). The state of this register bit changes with the status of the hardware
flow control. RTSn functions normally when hardware flow control is disabled.
logic 0 = automatic RTS flow control is disabled (normal default condition)
logic 1 = enable automatic RTS flow control.
5
EFR[5] Special character detect
logic 0 = Special character detect disabled (normal default condition)
logic 1 = Special character detect enabled. The SC68C652B compares each
incoming receive character with Xoff2 data. If a match exists, the received
data will be transferred to FIFO and ISR[4] will be set to indicate detection of
special character. Bit-0 in the X-registers corresponds with the LSB bit for the
receive character. When this feature is enabled, the normal software flow
control must be disabled (EFR[3:0] must be set to a logic 0).
4
EFR[4] Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and
MCR[7:5] can be modified and latched. After modifying any bits in the enhanced
registers, EFR[4] can be set to a logic 0 to latch the new values. This feature
prevents existing software from altering or overwriting the SC68C652B
enhanced functions.
logic 0 = disable/latch enhanced features. IER[7:4], ISR[5:4], FCR[5:4], and
MCR[7:5] are saved to retain the user settings, then IER[7:4] ISR[5:4],
FCR[5:4], and MCR[7:5] are set to a logic 0 to be compatible with SC16C554
mode. (Normal default condition.)
logic 1 = enables the enhanced functions. When this bit is set to a logic 1, all
enhanced features of the SC68C652B are enabled and user settings stored
during a reset will be restored.
3:0 EFR[3:0] Cont-3:0 TX, RX control. Logic 0 or cleared is the default condition.
Combinations of software flow control can be selected by programming these
bits. See Table 24.
SC68C652B_2
Product data sheet
Rev. 02 — 2 November 2009
© NXP B.V. 2009. All rights reserved.
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