SC68C652B Datasheet, PDF(1/43 Page) NXP Semiconductors – 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, and 68 mode mP interface

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SC68C652B Datasheet, PDF (1/43 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, and 68 mode mP interface

SC68C652B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte

FIFOs, IrDA encoder/decoder, and 68 mode ÂµP interface

Rev. 02 â 2 November 2009

Product data sheet

1. General description

The SC68C652B is a 2 channel Universal Asynchronous Receiver and Transmitter

(UART) used for serial data communications. Its principal function is to convert parallel

data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.

The SC68C652B is pin compatible with the SC68C2550B. The SC68C652B provides

enhanced UART functions with 32-byte FIFOs, modem control interface, DMA mode data

transfer, and infrared (IrDA) encoder/decoder. The DMA mode data transfer is controlled

by the FIFO trigger levels and the TXRDYn and RXRDYn signals. On-board status

registers provide the user with error indications and operational status. System interrupts

and modem control features may be tailored by software to meet speciï¬c user

requirements. An internal loopback capability allows on-board diagnostics. Independent

programmable baud rate generators are provided to select transmit and receive baud

rates.

The SC68C652B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,

and is available in the plastic LQFP48 package.

2. Features

I 2 channel UART with 68 mode (Motorola) ÂµP interface

I 5 V, 3.3 V and 2.5 V operation

I 5 V tolerant on input only pins1

I Industrial temperature range (â40 Â°C to +85 Â°C)

I Software compatible with industry standard 16C450, 16C550, and SC16C650

I Up to 5 Mbit/s baud rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V

I 32-byte transmit FIFO to reduce the bandwidth requirement of the external CPU

I 32-byte receive FIFO with error ï¬ags to reduce the bandwidth requirement of the

external CPU

I Independent transmit and receive UART control

I Four selectable receive and transmit FIFO interrupt trigger levels

I Automatic software (Xon/Xoff) and hardware (RTSn/CTSn) ï¬ow control

I Programmable Xon/Xoff characters

I Software selectable baud rate generator

I Standard modem interface or infrared IrDA encoder/decoder interface

I Supports IrDA version 1.0 (up to 115.2 kbit/s)

I Sleep mode

1. For data bus pins D7 to D0, see Table 27 âLimiting valuesâ.

▷