SC68C652B Datasheet, PDF (21/43 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, and 68 mode mP interface

NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
7.4 Interrupt Status Register (ISR)
The SC68C652B provides six levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. A lower level interrupt may be seen after servicing the higher level
interrupt and re-reading the interrupt status bits. Table 14 “Interrupt source” shows the
data values (bit 0 to bit 5) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Table 14. Interrupt source
Priority ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt
level
1
0
0
0
1
1
0
LSR (Receiver Line Status Register)
2
0
0
0
1
0
0
RXRDY (Received Data Ready)
2
0
0
1
1
0
0
RXRDY (Receive Data time-out)
3
0
0
0
0
1
0
TXRDY (Transmitter Holding
Register Empty)
4
0
0
0
0
0
0
MSR (Modem Status Register)
5
0
1
0
0
0
0
RXRDY (received Xoff signal)/
special character
6
1
0
0
0
0
0
CTS, RTS change-of-state
Table 15.
Bit
7:6
5:4
3:1
0
Interrupt Status Register bits description
Symbol Description
ISR[7:6]
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not
being used in the 16C450 mode. They are set to a logic 1 when the
FIFOs are enabled in the SC68C652B mode.
logic 0 or cleared = default condition
ISR[5:4]
INT priority bits 4:3. These bits are enabled when EFR[4] is set to a
logic 1. ISR[4] indicates that matching Xoff character(s) have been
detected. ISR[5] indicates that CTS, RTS have been generated. Note
that once set to a logic 1, the ISR[4] bit will stay a logic 1 until Xon
character(s) are received.
logic 0 or cleared = default condition
ISR[3:1]
INT priority bits 2:0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 14).
logic 0 or cleared = default condition
ISR[0]
INT status
logic 0 = an interrupt is pending and the ISR contents may be used
as a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
SC68C652B_2
Product data sheet
Rev. 02 — 2 November 2009
© NXP B.V. 2009. All rights reserved.
21 of 43