ADC1413S Datasheet, PDF (26/38 Pages) NXP Semiconductors – Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface

NXP Semiconductors
ADC1413S series
Single 14-bit ADC: serial JESD204A interface
11.6.3 Register description
11.6.3.1 ADC control registers
Table 18. Register SPI control (address 0003h)
Default values are highlighted.
Bit Symbol
Access Value
Description
7 to 2 -
-
111111 not used
1
ENABLE
R/W
ADC SPI control enable:
0
ADC does not get the next SPI command
1
ADC gets the next SPI command
0
-
-
1
not used
Table 19. Register Reset and Power-down mode (address 0005h)
Default values are highlighted.
Bit Symbol
Access Value
Description
7
SW_RST
R/W
reset digital part:
0
no reset
1
performs a reset of the digital part
6 to 2 -
-
00000 not used
1 to 0 PD[1-0]
R/W
Power-down mode:
00
normal (power-up)
01
full power-down
10
sleep
11
normal (power-up)
Table 20. Register Clock (address 0006h)
Default values are highlighted.
Bit Symbol
Access Value
7 to 5 -
-
000
4
SE_SEL
R/W
0
1
3
DIFF_SE
R/W
0
1
2
-
-
0
1
CLKDIV2_SEL
R/W
0
1
0
DCS_EN
R/W
0
1
Description
not used
select SE clock input pin:
select CLKM input
select CLKP input
differential/single-ended clock input select:
fully differential
single-ended
not used
select clock input divider by 2:
disable
enable
duty cycle stabilizer enable:
disable
enable
ADC1413S_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 8 June 2011
© NXP B.V. 2011. All rights reserved.
26 of 38