ADC1413S Datasheet, PDF (23/38 Pages) NXP Semiconductors – Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface

NXP Semiconductors
ADC1413S series
Single 14-bit ADC: serial JESD204A interface
Table 16.
W1
0
0
1
1
Number of bytes to be transferred
W0
0
1
0
1
Number of bytes transferred
1 byte
2 bytes
3 bytes
4 or more bytes
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incremented to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. The falling edge on pin CS in combination with a rising edge on pin SCLK determine
the start of communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can be vary in length but is always
a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on pin CS indicates the end of data transmission.
CS
SCLK
SDIO
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Instruction bytes
Fig 23. Transfer diagram for two data bytes (3-wire type)
Register N (data)
Register N + 1 (data)
005aaa086
ADC1413S_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 8 June 2011
© NXP B.V. 2011. All rights reserved.
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