ADC1412D Datasheet, PDF (26/40 Pages) NXP Semiconductors – Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1412D series
CMOS or LVDS DDR digital outputs
Table 14. LVDS DDR output register 2 …continued
LVDS_INT_TER[2:0]
Resistor value
101
100 Ω
110
81 Ω
111
60 Ω
11.5.3 DAta Valid (DAV) output clock
A DAta Valid (DAV) output clock signal is provided that can be used to capture the data
delivered by the ADC1412D. Detailed timing diagrams for CMOS and LVDS DDR modes
are provided in Figure 4 and Figure 5 respectively. In LVDS DDR mode, it is highly
recommended to shift ahead the DAV by 1 ns (bits DAVPHASE[2:0] = 0b100;
see Table 25).
11.5.4 OuT-of-Range (OTR)
An out-of-range signal is provided on pin OTRA for ADC channel A and on pin OTRB for
ADC channel B. The latency of OTRA/B is fourteen clock cycles. The OTR response can
be speeded up by enabling Fast OTR (bit FASTOTR = logic 1; see Table 30). In this
mode, the latency of OTRA/B is reduced to only four clock cycles (separately for each
ADC channel). The Fast OTR detection threshold (below full-scale) can be programmed
via bits FASTOTR_DET.
Table 15. Fast OTR register
FASTOTR_DET[2:0]
000
001
010
011
100
101
110
111
Detection level
−20.56 dB
−16.12 dB
−11.02 dB
−7.82 dB
−5.49 dB
−3.66 dB
−2.14 dB
−0.86 dB
11.5.5 Digital offset
By default, the ADC1412D delivers output code that corresponds to the analog input.
However, it is possible to add a digital offset to the output code via the SPI (bits
DIG_OFFSET; see Table 26).
11.5.6 Test patterns
For test purposes, the ADC1412D can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL; see Table 27). A custom test pattern can
be defined by the user (TESTPAT_USER; see Table 28 and Table 29) and is selected
when TESTPAT_SEL = 101. The selected test pattern is transmitted regardless of the
analog input.
ADC1412D_SER
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 6 August 2010
© NXP B.V. 2010. All rights reserved.
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