ADC1412D Datasheet, PDF (25/40 Pages) NXP Semiconductors – Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1412D series
CMOS or LVDS DDR digital outputs
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting
bit LVDS_CMOS to logic 1 (see Table 24).
3.5 mA
typ
VDDO
−
+
DAn_DAn + 1_P; DBn_DBn + 1_P
DAn_DAn + 1_M; DBn_DBn + 1_M
100 Ω
RECEIVER
+
−
OGND
005aaa112
Fig 22. LVDS DDR digital output buffer - externally terminated
Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver
side (Figure 22) or internally via SPI control bits LVDS_INT_TER (see Figure 23 and
Table 33).
3.5 mA
typ
VDDO
−
+
DAn_DAn + 1_P; DBn_DBn + 1_P
100 Ω
DAn_DAn + 1_M; DBn_DBn + 1_M
100 Ω
RECEIVER
+
−
OGND
Fig 23. LVDS DDR digital output buffer - internally terminated
005aaa113
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI and DATAI; see Table 32) in order to adjust the output logic voltage
levels.
ADC1412D_SER
Preliminary data sheet
Table 14. LVDS DDR output register 2
LVDS_INT_TER[2:0]
000
001
010
011
100
Resistor value
no internal termination
300 Ω
180 Ω
110 Ω
150 Ω
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 6 August 2010
© NXP B.V. 2010. All rights reserved.
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